1. Field of Invention
The present invention relates to circuits generally and more particularly to evaluating constrained circuit designs.
2. Description of Related Art
Modern circuit designs have led to increasingly complex timing constraints, expressed as timing constraint specifications in formats such as Synopsys Design Constraints (SDC). These constraints may include, for example, minimal/maximal delays and multi-cycle paths. Additionally some paths may be designated as “timing false paths” (or “false paths”) that should not be constrained in the optimization of the design (e.g., because the path relates to a system redundancy). As the original design is further refined in the design flow from RTL (Register Transfer Level) through post-P&R (Placement and Routing) netlist, the original timing constraint specification may no longer be valid. However, comparing different versions of constrained designs is often done line by line or constraint by constraint and without reference to a design-based standard that enables timing constraints to be compared for inconsistent and redundant constraints.
Thus, there is a need for improved verification and comparison of circuit design constraints.